EE 322 · Electrical Engineering

Microprocessors Design

Start with the control logic that gives a digital system memory: finite state machines, state transitions, and VHDL implementations.

Begin the FSM lesson

Weekly learning modules

Start with state

The first prepared lesson develops FSM reasoning through a three-state pulse generator and two serial pattern detectors. It connects the state diagram, transition table, timing, and VHDL for each design.

Week 1
Finite State Machines in VHDL

Open the detailed study article →

Further weeks will be added as they are prepared. The order here is a teaching path, not a claim about the official topic schedule.

Course context

Control meets hardware

In a microprocessor-based system, control decisions depend on what has already happened. The FSM is a compact way to express that memory and the next action in synthesizable hardware.

Official course: EE 322 · Microprocessors Design
Credit hours: 4
Prerequisites: EE 211, EE 221, CEE 201

Lab software · NexysVHDL 0.6.0 NexysVHDL Nexys A7. VHDL. No Vivado required. Write VHDL, simulate it, inspect waveforms and RTL, build the FPGA bitstream and program your Digilent Nexys A7-100T. Windows x64 and Apple-silicon macOS. VHDL→ Simulation→ FPGA→ Nexys A7 Install NexysVHDL

Official EE 322 curriculum

Relevant course learning outcomes

CLO 1.3

Model digital components of microprocessor-based systems using HDL at the RTL level.

CLO 2.2

Design control units and sequential systems using finite state machines for system control applications.

These are the official outcome wordings from the EE 322 curriculum. The Week 1 checks are formative teaching activities; their suggested alignment is identified separately in the lesson.