Finite State Machines in VHDL

Consider detecting two serial bits. The current bit alone cannot tell us whether 01 has arrived.

We do not store the entire history. We define states for the distinctions that affect future behavior.

The state register loads nextstate at a rising edge. Reset selects a known start.

A diagram shows the paths. A table checks every state and input. VHDL gives those rules to hardware.

Engineering check: these three must agree before simulation.

At each rising edge, advance once around three states.

Reset puts the register in S0. Let y be high only in S0.

Point to any diagram arrow; find the same row here.

type statetype is (S0, S1, S2);
signal state, nextstate: statetype;

state is the stored value. nextstate is the value computed for the next edge.

From the supplied 0430-divideby3FSM.vhd.

process(clk, reset) begin
  if reset = '1' then state <= S0;
  elsif rising_edge(clk) then
    state <= nextstate;
  end if;
end process;

Reset initializes; a rising edge transfers the calculated next state into memory.

Teaching copy: explicit STD_LOGIC comparison; original logic preserved.

nextstate <= S1 when state = S0 else
             S2 when state = S1 else
             S0;

Read the first line as S0 → S1, the second as S1 → S2, and the final branch as S2 → S0.

y <= '1' when state = S0 else '0';

Only S0 makes y high. There is no input on this output path.

The pulse repeats every three clocks. Its duty cycle is one third, not 50%.

Keep this architecture while the next two examples add a serial input.

One serial bit a arrives per clock. We want a detection pulse for the sequence 0 then 1.

From S1, another 0 keeps S1. A 1 completes the pattern and enters S2.

S2 on 0 returns to S1: that 0 can start another match.

when S1 =>
  if a = '1' then nextstate <= S2;
  else            nextstate <= S1;
  end if;

In S1, a 1 completes 01; a 0 leaves a useful trailing zero.

From the minimal teaching copy of 0431-patternMoore.vhd.

y <= '1' when state = S2 else '0';

Input a is absent. A change on a alone cannot change y.

Two overlapping detections: the output rises after edges 2 and 4.

S1 already remembers the first half: the last sampled bit was 0.

The output can be attached to the S1 transition instead of a new S2 state.

Only S1 with present input 1 detects the pattern.

when S1 =>
  if a = '1' then nextstate <= S0;
  else            nextstate <= S1;
  end if;

After a completing 1, the machine returns to S0. The output expression handles detection.

From the minimal teaching copy of 0432-patternMealy.vhd.

y <= '1' when (a = '1' and state = S1)
     else '0';

y can rise while S1 is held, before the next edge.

The assertions precede edges 2 and 4; the Moore assertions follow them.

Choose based on the output timing and interface you need.

• Giving a state a name without saying what it remembers.
• Leaving a state/input transition undefined.
• Comparing STD_LOGIC directly as if it were Boolean.
• Calling the divide-by-3 pulse a 50% duty-cycle clock.

Read the diagram, table, timing trace, and code against one another.

1. Understand the required behavior.
2. Identify what past information matters.
3. Define states for that information.
4. Draw the state diagram.
5. Build the transition table.

6. Choose Moore or Mealy outputs.
7. Write the clocked state register.
8. Write combinational next-state logic.
9. Write output logic.
10. Simulate reset, transitions, output timing, and overlaps.

For a serial input, decide what the machine must remember after each bit.

1. Draw a Moore state diagram.
2. Find a Mealy version.
3. Should 10101 count as one or two matches?

Discuss the meanings of your states before comparing diagrams.

10101 contains two matches. After detecting the first, the final 1 is already a useful prefix for the next.

EE 322 · Week 1

State is the useful part of the past

The three-state cycle records position in time. The detectors record a useful suffix of the bitstream.

In every design: state register → next-state logic → output logic.

Open detailed notes →